1. Field of the Invention
The present invention relates to a demodulator for demodulating a .pi./4 shifted QPSK signal.
2. Description of the Prior Art
FIG. 1 is a block diagram showing the structure of a quaternary-phase shift keying signal (hereinafter called "QPSK signal") decision/feedback type Costas loop, which is used as a conventional QPSK demodulator. Referring to FIG. 1, there are shown an input terminal 1 for receiving a QPSK signal, a first phase detector (hereinafter called "first PSD") 2 for detecting the phase difference between the input signal and a reference signal, a second phase detector (hereinafter called "second PSD") 3 for detecting the phase difference between the input signal and a signal 90.degree. shifted from the reference signal, a .pi./2 (90.degree.) phase-shifter 4 for phase-shifting the reference signal by 90.degree., a sign detector 5 for determining the sign of the output signals from the first and second PSDs 2, 3, a first multiplier 6 for multiplying the output signal of the first PSD 2 by a sign indicative of the output signal of the second PSD 3 outputted from the sign detector 5, a second multiplier 7 for multiplying the output signal of the second PSD 3 by a sign indicative of the output signal of the first PSD 2 outputted from the sign detector 5, a subtractor 8 for subtracting output signals from the first and second multipliers 6, 7, and a loop filter (hereinafter called "LF") 9 for band-limiting a frequency of an output signal of the subtractor 8, a voltage-controlled oscillator (hereinafter called "VCO") 10 for controlling the oscillating frequency in accordance with the output signal from subtractor 8 whose frequency is band-limited by the LF 9, and output terminals 11, 12 which supply the signals from phase detectors 2 and 3 to a data symbol detector 13 which determines the binary multisymbol data represented by the output signals of PSD's 2 and 3, and outputs such at terminal 15.
A description will now be made of the operation of the Costas loop demodulator. The transmitted QPSK signal to be received is applied to the input terminal 1. This input signal is conveyed to two branches, i.e., one for the first PSD 2 and the other for the second PSD 3. Then, the input signal applied to the first PSD 2 is phase-detected in accordance with an output reference signal from the VCO 10. Similarly, the input signal applied to the second PSD 3 is also phase-detected in accordance with an output reference signal that has been shifted by 90.degree. from the .pi./2 phase-shifter 4.
The conventional QPSK signal applied to terminal 1 is represented in accordance with the following equation (1): EQU s(t)=Asin{.omega..sub.s t+(2k(t)+1).pi./4+.theta..sub.i } (1)
In the above equation (1), the term A represents the amplitude of the input signal, the term .omega..sub.s represents its center angular frequency, the term .theta..sub.i represents its initial phase, and the term k(t) represents a modulating signal. The term k(t) will be defined as being 0, 1, 2, 3 (i.e., k(t)=0, k(t)=1, k(t)=2, k(t)=3 corresponding to the binary symbol pairs (1,1), (1,0), (0,0), (0,1) of the modulating signal having two channels P and Q, which signal changes for each clock period In other words, binary pairs 11, 10, 00, and 01 are represented by s(t) having phases of .pi./4, 3.pi./4, -3.pi./4, and -.pi./4 respectively.
On the other hand, the output signal of the VCO 10 is represented by the following equation (2): EQU V(t)=2cos(.omega..sub.v t+.theta..sub.0) (2)
In the equation (2), the coefficient 2 represents the amplitude of the output signal from the VCO 10, the term .omega..sub.v designates its center angular frequency, and the term .theta..sub.0 shows its initial phase.
Here, the output signal of the first PSD 2 is given by the low-frequency component of the product of the above-described two signals, i.e., s(t) and V(t). This output signal will be represented as P.sub.1 (t) in accordance with the following equation (3): EQU P.sub.1 (t)=Asin{(.omega..sub.s -.omega..sub.v)t +(2k(t)+1)#/4+(.theta..sub.i -.theta..sub.0)) (3)
In addition, when .omega..sub.s =.omega..sub.v in the above equation (3), this equation is rewritten as the equation (4). The output signal at this time is represented as in FIG. 2(a). EQU P.sub.1 (t)=Asin{(2k(t)+1).pi./4 +(.theta..sub.i -.theta..sub.0)}(4)
On the other hand, the output signal of the .pi./2 phase-shifter 4 is given by the following equation (5): EQU V.sub.d (t)=2sin(.omega..sub.v t+.theta..sub.0) (5)
The signal represented by the equation (5) is applied to the second PSD 3. The output signal obtained when .omega..sub.s =.omega..sub.v is represented as in FIG. 2(b) by the following equation (6): EQU P.sub.2 (t)=Acos{(2k(t)+1).pi./4 (6)
Now, the output signal of the first PSD 2 is conveyed to two branches, i.e., one for the first multiplier 6 and the other for the sign detector 5. Similarly, the output signal of the second PSD 3 is also conveyed to two branches, i.e., one for the second multiplier 7 and the other for the sign detector 5.
A description will now be made of the construction of the sign detector 5 with reference to FIG. 3. The sign detector 5 comprises two input signal terminals 5a, 5b, two comparators 5c, 5d and two output signal terminals 5e, 5f. Each of the comparators to be described herein is used to determine a sign of the input signal. When the input signal is represented by Y(t), their logic functions can be expressed by the following equation (7): ##EQU1##
In the above-described manner, a sign of the signal represented by the equation (6) is applied to the other of the inputs of the first multiplier 6, while a sign of the signal represented by the equation (4) is applied to the other of the inputs of the second multiplier 7.
Assuming now that the output signal of the first multiplier 6 is represented by V.sub.M1 (t), the output signal of the first multiplier 6 is expressed as in FIG. 2(c) by the following equation (8): ##EQU2##
Similarly, assuming that the output signal of the second multiplier 7 is represented by V.sub.M2 (t), the output signal of the second multiplier 7 is represented as in FIG. 2(d) by the following equation (9): ##EQU3## Next, when the equation (9) is subtracted from the equation (8) in the subtractor 8, the resultant output signal e.sub.0 (t) is represented as in FIG. 2(e) by the following equation (10) regardless of the values of k(t): ##EQU4##
This e.sub.0 (t) is referred to as the phase error voltage and is applied to a frequency control terminal of the VCO 10 through the LF 9(band-limitation processing). This e.sub.0 (t) controls the frequency of VCO 10 such that .theta..sub.i =.theta..sub.0 in the VCO 10. the output signal of the VCO 10 at that time is represented in accordance with the following equation (11): EQU V(t)=2cos(.omega..sub.s t+.theta..sub.i +n.pi./2) (11)
where n=0, 1, 2, 3
This V(t) is referred to as the recovered reference carrier (reference signal) and is also in synchronization with the input signal s(t). The term n.pi./2 represents the four possible phases of the output signal V(t) synchronized with the input signal s(t) as shown in FIG. 2(e). The reference character n has an equal probability of falling into any one of 0, 1, 2 and 3.
Incidentally, the above-described QPSK signal decision/feedback type Costas loop is disclosed, for example, in Gardner, "Phaselock Techniques", p. 223, John Wiley & Sons.
Since the QPSK signal decision/feedback type Costas loop as a conventional QPSK demodulator is constructed as described above, when a .pi./4 shifted QPSK signal is inputted at terminal 1, the output signal of the VCO will alternate between the following equations (11) and (12) with each clock period. EQU V(t)=2cos(.omega..sub.x t+.theta..sub.i +n.pi./2) (11)
where n=0, 1, 2, 3 EQU V(t)=2cos(.omega..sub.s t+.theta..sub.i +n.pi./2+.pi./4) (12)
where n=0, 1, 2, 3.
The conventional Costas loop demodulator therefore cannot be used to demodulate a .pi.4/shifted QPSK signal as the output signal V(t) cannot be synchronized with the .pi./4 shifted QPSK input signal because of the alternating constellation shift of this signal.
The .pi./4 shifted QPSK signal modulation system is now described with reference to FIG. 5. In normal QPSK modulation, a modulated carrier signal has one of four phases which denote a binary data pair, i.e. 00, 01, 10, or 11. Two possible choices for the four phase angles are 0, .+-..pi./2, .pi., or .+-..pi./4, .+-.3.pi./4. In FIG. 5, o represents the former and .DELTA. represents the latter choice, or "signal constellation". However, symbol transitions of 180.degree., i.e. from .pi./2 to -.pi./2, such as for a data sequence 1100, require the carrier to pass through zero amplitude, meaning that a wide dynamic range amplifier such as a class A amplifier is needed. However, class A amplifiers operate very inefficiently.
In a .pi./4 shifted QPSK scheme, the signal phases alternate between 0, .+-..pi./2, .pi. (o), and .+-..pi./4, .+-.3.pi./4 (.DELTA.) for each successive symbol pair. Thus, the carrier must pass through only the paths indicated by the arrows between the phases .largecircle. and .DELTA. and not through zero amplitude, so that more efficient amplifiers such as class B or class C can be used in the transmitter.